The first Agilex 7 FPGA R-Tile to support PCIe 5.0 and CXL functions

     Intel's Programmable Solutions Business Group announced that volume delivery of the Intel Agilex 7 R-tile is underway. The device is the first FPGA with PCIe 5.0 and CXL capabilities, and the only one with the hardened intellectual property (IP) required to support these interfaces. Agilex 7's configurable and scalable architecture enables customers to quickly deploy customized technologies that are hardware-accelerated to scale based on their specific needs, reducing overall design costs, shortening development processes and speeding execution to achieve optimal data center performance.

     "Customers demand cutting-edge technology to deliver the scalability and customization they need to effectively manage their current workloads while being able to adapt functionality as their needs change," said Shannon Poulin, vice president and general manager of Intel's Programmable Solutions Group. Intel Agilex products support programmable innovation at the speed, power consumption and functionality required by our customers, while providing flexibility and resilience for their future growth. For example, customers are using R-Tile with PCIe 5.0 and CXL capabilities to speed up software and data analysis, reducing processing time from hours to minutes.

     Faced with time, budget, and power constraints, organizations in various industries, including data centers, telecommunications, and financial services, see FPGas as flexible, programmable, and efficient solutions. With Agilex 7 R-Tile, customers can seamlessly interface FPGas with processors such as fourth-generation Intel Xeon Scalable processors and speed up targeted data center and scientific computing workloads with the highest bandwidth processor interface.

     Agilex 7 R-Tile FPGA has leading technology capabilities. Compared with other FPGA products, the PCIe 5.0 bandwidth of each port is two times faster and the CXL bandwidth is four times faster. According to a white paper published by Meta and the University of Michigan, adding an FPGA with CXL memory to a server based on a fourth-generation Intel Xeon scalable processor, along with efficient memory page management techniques for transparent page placement (TPP), can improve Linux performance by 18%.

     In addition, UnifabriX demonstrated its CXL-enabled smart memory nodes in several performance benchmarks, including one that showed a 28% increase in the HPCG (High performance Conjugate gradient) benchmark score by doubling the number of Xeon 4 scalable processor cores available for scientific computing workloads.