Silicon Labs PCI Express clock jitter calculation tool simplifies timing design

     Silicon Labs has announced the release of a free software tool that enables engineers to quickly and easily calculate PCI Express(PCIe) clock jitter results from oscilloscope data files in a few simple clicks, making it easy to verify PCIe specification compatibility and reduce system development time. Silicon Labs' Clock jitter Calculation tool is the industry's first standard jitter calculator available for PCIe 1.0, 2.0, 3.0, and 4.0 specifications, and is freely available to anyone working on the development of popular PCIe architecture applications. Designed to support PCIe public clock and separate clock architectures, the tool is open to the industry and is not limited to clock products from Silicon Labs.

     Since the birth of PCIe as a serial interconnect interface for desktop PCS a decade ago, the PCIe standard has evolved over three generations and is widely used in blade servers, storage, embedded computing, IP gateways, industrial systems, and consumer electronics. PCIe technology has also been used in FPGA and SoC devices, providing a flexible, high-performance data transfer method for transferring data within the system. Because the PCIe specification specifies a reference clock with 100MHz, ±300ppm frequency stability, some FPGA and SoC designs may internally run reference clock frequencies up to 250MHz, making clock jitter evaluation a key design consideration.

     Filter mask and jitter calculations in PCIe technology are often misunderstood during development. Most oscilloscopes are not equipped with the necessary filter mask to get the correct PCIe clock jitter calculation, which creates confusion as to why the measurement results do not match the data book specifications. Developers often report PCIe jitter measurements that are higher than the clock data manual specification, which is an incorrect measurement rather than a design issue. Silicon Labs, a leading provider of PCIe clock products, has created the PCIe jitter Calculation Tool to address these needs, providing hardware designers with a downloadable utility to quickly determine if a clock under test meets PCIe jitter requirements.

     Silicon Labs' clock jitter calculation tool for PCIe technology has an intuitive graphical user interface that guides developers to calculate clock jitter from oscilloscope data files in just a few simple steps. The tool includes all filter masks defined by the PCI-SIG for PCIe 1.0, 2.0, 3.0, 4.0 common clock and split clock reference architectures, and supports independent spread spectrum (SRIS) and non-spread spectrum (SRNS) technologies. Users can know the jitter results in a concise and easy-to-read summary format, eliminating the need to work with guesswork, ensuring that the system design meets PCIe specifications and has sufficient jitter tolerance. For more convenience, users can also save the jitter calculation results as PDF files for future reference.

     In related news, Silicon Labs has announced that its clock generators and buffers meet PCIe 4.0 specification requirements. All relevant product data sheets have been updated to comply with PCI Express Basic Specification 4.0 rev 0.5. James Wilson, Director of timing Product Marketing at Silicon Labs, said: "To simplify the task of timing design, we developed a clock jitter calculation tool to make obtaining PCIe jitter measurements as fast, easy and accurate as possible. As a service to the industry, we are making this helpful clock jitter calculator freely available to all developers working with the PCIe data bus standard, regardless of their clock IC vendor."