Microsemi releases Libero SoC v11.8 software to provide FPGA designers with mixed-language simulation and best-in-class debugging capabilities

     Microsemi Corporation, a leading provider of differentiated semiconductor technology solutions in terms of power consumption, safety, reliability and performance, has released the latest version of Libero system-on-a-chip (SoC) software, v11.8. This is a comprehensive programmable logic device (FPGA) design tool with important performance improvements such as mixed-language simulation, best-in-class debugging, and a new netlist view. In addition, Microsemi Corporation provides a free License for users to evaluate Microsemi's Flash-based FPGA and SoC FPGA devices.

     The Microsemi Libero SoC Design Kit includes Mentor Graphics ModelSim Simulator, which verifies hardware Description language (HDL) code line by line. Simulation can be performed at any level: behavioral (pre-synthesis), structural (post-synthesis), and inverse dynamic simulation. The easy-to-use graphical user interface allows users to quickly identify and debug problems. Libero SoC v11.8 now also includes ModelSim Microsemi Pro, which allows users to simulate in mixed language environments and can increase simulation time by 20% compared to previous versions.

     Jim Davis, vice President of software engineering at Microsemi , said: "The new release Libero SoC v11.8 features significant improvements where the integrated ModelSim ME Pro provides mixed-language simulation support for VHSIC Hardware Description Language (VHDL), Verilog, and SystemVerilog. Enables customers to target a wide variety of IP designs without having to worry about mixing multiple languages. The new version also includes the latest SmartDebug enhancements, such as the FPGA Hardware Breakpoint (FHB) feature, which is unique to the Meko Semi FPGA. The FHB feature allows users to set breakpoints in the design and step through the clock cycle, which greatly improves visibility and reduces debugging time."

     While breakpoints have always been used in embedded software, they can now be used to support FPGA logic debugging capabilities. This can increase the productivity, usability and efficiency of FPGA designs to get to market quickly, especially during the product validation phase, which is the longest in the product development cycle. These SmartDebug enhancements complement existing debugging capabilities, eliminating the need for an integrated logic Analyzer (ILA) and providing a new way to debug state, memory, and serial/unstring (SerDes) transceivers of FPGA devices.

     The Microsemi  Libero SoC v11.8 is particularly suited for FPGA design for a variety of applications in the aerospace, defense, security, communications, data center, industrial and automotive markets. It also includes a host of additional features, such as a new netlist view that can see through different internal structures, a new constraint management feature with module streams and input/output (I/O) consultants, and a 20% uptime improvement in its SmartTime user interface, which also supports Windows 10.

     To make the solution widely available, Libero SoC v11.8 also comes with a new 60-day free evaluation license to evaluate Microsemi Corporation's Flash-based FPGA and SoC reference designs, as well as tutorials and application guides. In response to growing customer demand for Megro's easy-to-learn design kits, the new evaluation license provides an easy way for customers to quickly get started designing Libero SoCs

     Aberdeen's market analysis suggests that about 50 billion machines will be connected by 2020. These machines must not only be safe, but also secure at the device, design and system levels. Leveraging Microsemi Corporation's expertise in security, Libero SoC v11.8 also includes the company's Secure Production Programming Solution (SPPS), which generates and injects encryption keys and configuates bitstreams to prevent overbuild, cloning, reverse engineering, virus code insertion, and other security threats.